ns am confused about the definition of native size. I review that the word dimension of a processor is that data bus width. Favor an 8 little bit processor has an 8 bit large data bus. I newly read that the maximum dimension of the digital address an are is identified by word dimension i.e. If the word size is n bits the max digital address room is 2^n -1. But I constantly thought that maximum online address an are is identified by deal with bus width i.e. One n bits broad address bus can attend to maximum 2^n bytes. So, what is true?

Also, is this pertained to pointers together an n bit data bus is qualified of carrying just an n little bit address. So, maximum 2^n bytes deserve to be accessed via pointers.

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I"ll an initial say that few of your man probably originates from the reality that points were less complicated a few decades ago and your knowledge of state is based on these simpler machines.

I am confused about the definition of word size.I review that the word dimension of a processor is its data bus width. Like an 8 little bit processor has an 8 bit broad data bus.

Definitely not. Data bus with is completely unrelated come this. The word size (which has never really been a precise term) that a processor is ideal loosely defined as the largest organic size for arithmetic which is typically the dimension of the it is registered in the machine. This is quite commonly the broad of the data path (which is distinctly various from the data bus). The data course is merely the width of the ALUs. The word size is frequently the exact same as the tip size.

I freshly read the the maximum size of the online address room is figured out by word dimension i.e. If the word size is n bits the max virtual address an are is 2^n -1. But i constantly thought the maximum virtual address room is figured out by resolve bus broad i.e. An n bits broad address bus can address maximum 2^n bytes. So, what is true?

No. The dimension of the virtual address space is simply figured out by the variety of bits in the virtual page number of the web page table (and the TLB). On existing amd64 based machines, only 48 bits of the virtual attend to are useable. The upper 16 room a sign extension of little 47. On present amd64 machines, the physical deal with size is 52 bits. These physical address bits room the ones the are sent on the bus. Though also the ax bus is really incorrect. Nearly all links are point-to-point (DDRx dram is one exception) and use a packetized style (header + payload) instead of attend to wires and data wires.

Also, is this regarded pointers as an n little bit data bus is capable of carrying just an n little bit address. So, preferably 2^n bytes deserve to be accessed via pointers.

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Many (almost every even) machines that have a separate deal with bus, use an deal with bus that is narrower 보다 the the number of address bits. These bits are simply separation up and sent across the bus utilizing multiple clock cycles. DDRx theatre is one more example the this.